Superconducting digital technology has provided computing and/or communications resources that benefit from unprecedented high speed, low power dissipation, and low operating temperature. For decades, superconducting digital technology has lacked random-access memory (RAM) with adequate capacity and speed relative to logic circuits. This has been a major obstacle to industrialization for current applications of superconducting technology in telecommunications and signal intelligence, and can be especially forbidding for high-end and quantum computing. All concepts currently considered for superconducting memory have been based on quantization of magnetic flux quanta in a superconducting inductive loop. Such memories can be readily adapted to high speed register files given a foundry process with adequate yield, but can never achieve the integration density of complementary metal-oxide semiconductor (CMOS), as they are fundamentally limited by the size of the inductive loop. One hybrid memory solution has been proposed where the memory core implements CMOS technology and the bit-line detection is performed with Josephson devices. However, such a configuration yields only nominally higher performance than standard CMOS and suffers from relatively high power dissipation for a cryogenic environment.